1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method form forming a self-aligned contact (SAC).
2. Description of Related Art
As semiconductor device integration continuously increases, the device dimension is necessary to be accordingly reduced. Thus, a contact opening in the device needs a more precise alignment to prevent an improper electrical coupling to the adjacent device element from occurring as an metallic material is filled into the contact opening. The improper electrical coupling usually causes a short circuit in the device. For example, a contact opening is desired to expose a interchangeable source/drain region but it may also expose a portion of a gate structure if a misalignment occurs. When the misaligned contact opening is filled with metallic material, the interchangeable source/drain and the gate structure are improperly coupled, resulting in a short circuit.
In order to prevent the circuit from occurring, a self-aligned contact technology is developed. A conventional process to form a self-aligned contact (SAC) opening includes forming a cap layer on a gate, which is formed on a semiconductor substrate. A spacer is formed on each sidewall of the gate and the cap layer. A dielectric layer is formed over the substrate, and a contact opening is formed in the dielectric layer. Here, the spacer and the cap layer have to include different insulating material from a material used for forming the contact dielectric layer so as to obtain a proper etching selectivity to only etch the dielectric layer. In this manner, if a misalignment occurs, the contact opening geometrically overlaps with the gate, but the gate is not actually exposed due to protection from the spacer and the cap layer. When a contact plug is formed to fill the contact opening, the short circuit is avoided. This is the main idea of the SAC technology.
Typically, the dielectric layer includes silicon oxide so that the cap layer and the spacer usually include silicon nitride to obtain a desired etching selectivity. In this structure, a stress consequently exits between the spacer made of silicon nitride and the gate, causing a defect of the gate, and further resulting in a current leakage. Conventionally, in order to solve the solve the stress issue, a thin oxide layer is proposed to form in between the spacer and the gate.
However, during the etching, process to form the SAC opening, since the thin oxide layer also includes same material as that of the dielectric layer, a portion of the thin oxide layer is simultaneously etched. Moreover, some native oxide after the etching process remains in the etched portion of the thin oxide layer. The native oxide is cleaned by rinsing with HF acid solution, which may further remove a portion of the thin oxide layer. As a result, a clearance occurs between the gate and the spacer, in which the clearance exposes a portion of the gate within the SAC opening. When metallic material is filled into the SAC opening, a short circuit occurs again, even though the opening is formed by the SAC technology.